Gate Level Netlist Analysis
Automated toolset for quantitative analysis of chips to assist in the detection of intentional and unintentional design flaws
Massive outsourcing of the chip design and manufacturing processes (fabless model) as well as increased demand for commercial and custom off the shelf components (COTS) chips including system-on-chip (SoC) in the military, healthcare, consumer electronics, space, automotive, and IoT sectors, have raised reliability and security issues. Aiding to the cause is the increasing complexity of chip design and shorter Time-To-Market (TTM), which has led to the inclusion of third-party designers and/or vendors in the electronic supply chain. Subsequently, the possibility of insertion of intentional (hardware Trojan, backdoors) and unintentional flaws at various levels of the chip production process increased significantly, which has led the customers of third-party chips to question their trustworthiness. Techniques for the detection of such flaws accurately require the analysis of chips at various levels of abstraction. Mature electronic design and automation (EDA) tools with better coverage can detect design flaws at the register-transfer level (RTL) of abstraction. However, end-users such as original equipment manufacturers (OEM) of chips may have access to the gate level of design or the RTL code provided by third-party vendors may not match their design specifications. Furthermore, security measures implemented at the RTL may not propagate to the synthesized gate level of the design. Consequently, security validation and detection of design flaws at the gate level become extremely important.
Silicon Assurance’s Analyz™ – N toolset aid end-users such as OEMs by providing quantifiable security assurance of a chip design under the zero trust model. Furthermore, the toolset can support our end users by extracting the high-level circuit description from the low-level netlist, without the availability of the original design. Analyz™ – N incorporates six proprietary tools. The unique features of the toolset are:
Accurate Translation
Generate accurate RTL source code from gate level netlist of a chip
Scalability
Detect flaws in large scale SoC designs
Speed
Time taken to translate the chip design is relative to the complexity of the logic being recovered
Automatic RTL source code generation from gate-level netlist
Silicon Assurance’s Analyz™ – N toolset addresses user-specified security challenges by analyzing the chip design at the gate level of abstraction. The toolset takes the gate level netlist of a large chip such as an SoC and detects intentional and unintentional flaws in it. The toolset also has the additional functionality of automatically converting the gate level netlist of the design to a human-readable RTL source code. Currently, no automated tool exists in the market that can carry out such functionalities.
